`timescale 1ns/1ns
module sram_test( 
	input  				clk_in,
    input               rst_n,
    // output              web,
    // output   [14:0]     addr,
    // output   [31:0]     wdata,
    // input    [31:0]     rdata,
    output              sram_led
);								 

    reg detect;
	reg [15:0] cnt;
    reg flag;
	wire CRST_N;
	reg [18:0] r_filter_bt0;
	wire reset;
    reg [31:0] wdata_emb;
    wire [31:0] rdata_emb;
    wire              web;
    reg   [14:0]     addr;
    reg   [31:0]     wdata;
    wire    [31:0]     rdata;
 
    assign sram_led      = detect;
	assign CRST_N 		 = rst_n;
	assign reset 		 = (r_filter_bt0 == 19'h3C)? 1'b1:1'b0;	//10*100ns=1us
    assign web           = cnt[15];

	always @(posedge clk_in or negedge reset) begin
		if(!reset) begin
			cnt <= 16'b0000_0000_0000_0000;
        end
        else if(cnt == 16'b1111_1111_1111_1111) begin
			cnt <= 16'b0000_0000_0000_0000;
        end
		else
			cnt <= cnt + 1'b1;
	end
	
	always @(posedge clk_in or negedge rst_n)
	begin
		if (!rst_n)
			r_filter_bt0 <=19'h0;
		else 
		if(r_filter_bt0 >= 19'h3C)	//10*100ns=1us
			r_filter_bt0 <=19'h3C;
		else	        
			r_filter_bt0 <= r_filter_bt0 +1'b1;
	end  

	always @(posedge clk_in or negedge reset) begin
		if(!reset)
			wdata <= 32'h0b0b0b0b;
		else if(cnt[0] == 1'b0)
			wdata <= 32'h0a0a0a0a;
		else
			wdata <= 32'h0b0b0b0b;
	end

    //flag为1开始检测sram读是否正常
	always @(posedge clk_in or negedge reset) begin
		if(!reset)
			flag <= 1'b0;
		else if(cnt > 16'b1000_0000_0000_0000 && cnt < 16'b1111_1111_1111_1110)
			flag <= 1'b1;
		else
			flag <= 1'b0;
	end
	
	sram_v1 u_sram(
		.clk(clk_in),
		.web(cnt[15]),
		.ceb(1'b0),
		.bl(4'b0000),
		.addr(cnt[14:0]),
		.wdata(wdata),
		.dout(rdata)
	);

    //判断写入数据和读出数据是否符合，若有一个地址不符合LED8熄灭
	always @(posedge clk_in or negedge reset) begin
		if(!reset)
			detect <= 1'b0;
		else if((flag == 1'b1) && (((cnt[0] == 1'b0) && (rdata != 32'h0a0a0a0a)) ||
				((cnt[0] == 1'b1) && (rdata != 32'h0b0b0b0b))))
			detect <= 1'b1;
	end
endmodule